Systems · Reverse Engineering · FPGA
Computer engineer working close to the hardware: undocumented protocols, real-time signal processing in programmable logic, and the kind of problem that is only solved by measuring it. Currently a core software developer at Ágata Technology, and building toward embedded and defence systems.
Repository metadata below — language, stars, last push — is read live from the GitHub API, so it is never out of date with the code.
Other people's projects, made better.
Every idle client burned about 0.7 of a CPU core from one release onward, and the cost multiplied by the number of open sessions. Bisected against the last good version as a control and reproduced by starting the binary from a shell and sending it nothing at all. Fixed upstream; on closing, the maintainer wrote that “the diagnosis in this thread did the hard part”.
Datacentre GPUs such as the P100 and V100 expose a single performance state, so the tool had nothing to switch them to. This adds a clock-based fallback: where setting a P-state fails, read each GPU's lowest supported core and memory clocks and idle there instead. Open.
Bytes of source across the projects listed above, markup and build glue excluded.
Read per repository from the API, so this is real source rather than repository size — counting the latter would put a folder of datasets above every line of C here. LaTeX, HTML and build files are left out for the same reason: the thesis alone carries half a megabyte of typesetting. Even then, bytes are not where the work went. A Flex/Bison parser is 60 KB and an RTL design is smaller still, and the reverse-engineering work lives in private repositories that this cannot see.
What the work above actually runs on.